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PAPERS

1996年の研究業績

1996年（平成8年）の研究業績

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学術論文

  1. Hiroyuki KOBAYASHI, Hitoshi KIYA,
    "A Design Method for Oversampled DFT Filter Banks with the Minimum Delay",
    IEICE Trans., Vol. J79-A, No. 11, pp. 1801-1807, 1996-11-01. [webpage] [Local]
  2. Masahiro IWAHASHI, Noriyoshi KAMBAYASHI, Hitoshi KIYA,
    "A Motion Compensation of Scalable Decoder for Drift Reduction",
    IEICE Trans., Vol. J79-A, No. 1, pp. 125-134, 1996-01-01. [webpage] [Local]
  3. Shogo MURAMATSU, Hitoshi KIYA,
    "A New Factorization Technique for the Generalized Linear-Phase LOT and Its Fast Implementation",
    IEICE Trans. Fundamentals, Vol. E79-A, No. 8, pp. 1173-1179, 1996-08-01. [webpage] [Local]
  4. Masahiro IWAHASHI, Noriyoshi KAMBAYASHI, Hitoshi KIYA,
    "A Scalable Decoder with Reduced Hardware Complexity",
    IEICE Trans., Vol. J79-A, No. 7, pp. 1324-1329, 1996-07-01. [webpage] [Local]
  5. Hisashi SAKANE, Hitoshi KIYA,
    "A Super-Resolution Method Based on the Discrete Cosine Transform",
    IEICE Trans. Fundamentals, Vol. E79-A, No. 6, pp. 768-776, 1996-06-01. [webpage] [Local]
  6. Shogo MURAMATSU, Hitoshi KIYA,
    "An Efficient Structure of GenLOT for Finite-Duration Sequences and Its Application to M-Band Discrete-Time Wavelet Transforms",
    IEICE Trans., Vol. J79-A, No. 12, pp. 1966-1976, 1996-12-01. [webpage] [Local]
  7. Masahiro IWAHASHI, Noriyoshi KAMBAYASHI, Hitoshi KIYA,
    "Bit Reduction of DCT Basis for Transform Coding",
    IEICE Trans., Vol. J79-B-I, No. 53, pp. 572-581, 1996-08-01. [webpage] [Local]
  8. Takeo YOSHIDA, Hitoshi KIYA, Sachio NAITO,
    "Design Verification for Register Transfer Level Design by Input Label Sets and Control Conditions",
    IEICE Trans., Vol. J79-D, No. 1, pp. 28-40, 1996-01-01. [webpage] [Local]
  9. Hitoshi KIYA, Hiroyuki KOBAYASHI,
    "Oversampled Filter Banks Based on Polyphase Submatrices",
    IEICE Trans., Vol. J79-A, No. 9, pp. 1525-1534, 1996-09-01. [webpage] [Local]
  10. Katsushige MATSUBARA, Kiyoshi NISHIKAWA, Hitoshi KIYA,
    "Pipelined Adaptive Filters Based on Delayed LMS Algorithm",
    IEICE Trans., Vol. J79-A, No. 5, pp. 1050-1057, 1996-05-01. [webpage] [Local]
  11. Kazunobu TOGUCHI, Hiroyuki KOBAYASHI, Hitoshi KIYA,
    "Subband Adaptive Filters with Perfect Reconstruction DFT Filter Banks",
    IEICE Trans., Vol. J79-A, No. 8, pp. 1385-1393, 1996-08-01. [webpage] [Local]

国際学会論文

  1. Kuniyuki KAJITA, Hiroyuki KOBAYASHI, Shogo MURAMATSU, Akihiko YAMADA, Hitoshi KIYA,
    "A Design Method of Oversampled Paraunitary DFT Filter Banks Using House-Holder's Factorization",
    EURASIP European Signal Processing Conference, 1996-09-01.
  2. Shogo MURAMATSU, Hitoshi KIYA,
    "A New Design Method of Linear-Phase Paraunitary Filter Banks with an Odd Number of Channels",
    EURASIP European Signal Processing Conference, 1996-09-01.
  3. Shigenori KINJO, Hiroshi OCHI, Hitoshi KIYA,
    "A New Two-Dimensional Parallel Block Adaptive Digital Filter",
    IEEE Midwest Symposium on Circuits and Systems, 1996-08-01.
  4. Hisashi SAKANE, Kiyoshi NISHIKAWA, Hitoshi KIYA,
    "A Super-Resolution Method Based on the Discrete Cosine Transforms",
    EURASIP European Signal Processing Conference, 1996-09-01.
  5. Kuniyuki KAJITA, Hiroyuki KOBAYASHI, Shogo MURAMATSU, Akihiko YAMADA, Hitoshi KIYA,
    "Design Methods for Oversampled DFT Filter Banks",
    International Technical Conference on Circuits/Systems, Computers and Communications, 1996-07-01.
  6. Takeshi UCHIDA, Hitoshi KIYA, Akihiko YAMADA,
    "Generating a Hierarchical Simulation Model on the Basis of Functional Model of Register Transfers",
    IEEE International Symposium on Circuits and Systems, 1996-05-01.
  7. Katsushige MATSUBARA, Kiyoshi NISHIKAWA, Hitoshi KIYA,
    "Pipelined Adaptive Filters Based on Two-Dimensional LMS Algorithm",
    International Technical Conference on Circuits/Systems, Computers and Communications, 1996-07-01.
  8. XiaoXia ZOU, Shogo MURAMATSU, Hitoshi KIYA,
    "The Generalized Overlap-Add and Overlap-Save Methods Using Discrete Sine and Cosine Transforms for FIR Filtering",
    IEEE International Conference on Signal Processing, 1996-10-01.

学会講演論文

  1. Hiroyuki KOBAYASHI, Hitoshi KIYA,
    "A Design Method of Low Delay DFT Filter Banks",
    General Conference of IEICE, pp. A-204, 1996-03-01.
  2. Seiji WATANABE, Nobuo FUJII, Hitoshi KIYA,
    "A Design Method of Multistage Rate Converteres based on Adaptive Filters",
    Society Conference of IEICE, pp. A-93, 1996-09-01.
  3. Seiji WATANABE, Hitoshi KIYA, Nobuo FUJII,
    "A Design Method of Multistage Rate Converteres based on Adaptive Filters",
    IEICE Digital Signal Processing Symposium, pp. B3-3, 1996-11-01.
  4. Seiji WATANABE, Kiyoshi NISHIKAWA, Nobuo FUJII, Hitoshi KIYA,
    "A Design Method of Rate Converters based on Adaptive Filters",
    Technical Report of IEICE, pp. DSP96-61, 1996-07-01.
  5. Keisuke NAKAZONO, Takeshi UCHIDA, Hitoshi KIYA, Akihiko YAMADA,
    "A Unit Selection Method for Multiplications with Various Word Lengths",
    Technical Report of IEICE, pp. VLD96-14, 1996-06-01.
  6. XiaoXia ZOU, Hisashi SAKANE, Hitoshi KIYA,
    "Algorithm for the DFT-based Super-resolution Method using",
    General Conference of IEICE, pp. A-135, 1996-03-01.
  7. Katsushige MATSUBARA, Kiyoshi NISHIKAWA, Hitoshi KIYA,
    "An Architecture of Pipelined Adaptive Filters Using A New Look-ahead transformation",
    Society Conference of IEICE, pp. A-94, 1996-09-01.
  8. Shogo MURAMATSU, Hitoshi KIYA,
    "An Efficient Structure of Generalized LOT for Finite-Duration Sequences : Efficient implementation of a symmetric extension method",
    Technical Report of IEICE, pp. DSP96-62, 1996-07-01.
  9. Takeshi UCHIDA, Hitoshi KIYA, Akihiko YAMADA,
    "An Evaluation of the Simulation Model with a Hierarchy in terms of Abstraction Levels",
    Society Conference of IEICE, pp. A-65, 1996-09-01.
  10. Yasuhiro HARADA, Shogo MURAMATSU, Hitoshi KIYA,
    "Evolution of Linear-Phase Orthonormal M-band DTWT using the modified GenLOT",
    General Conference of IEICE, pp. SA-4--5, 1996-03-01.
  11. Takeshi UCHIDA, Hitoshi KIYA, Akihiko YAMADA,
    "Generating a Hierarchical Simulation Model on the Basis of Functional Model of Register Transfers",
    IPSJ Technical Reports, pp. DA79-4, 1996-02-01.
  12. XiaoXia ZOU, Shogo MURAMATSU, Hitoshi KIYA,
    "Implementation of Sampling Rate Conversion with Fewer Delay",
    Technical Report of IEICE, pp. DSP96-104, 1996-12-01.
  13. Takuya YAMAUCHI, Hiroyuki KOBAYASHI, Hitoshi KIYA,
    "Low Delay Oversampled Filter Banks",
    Technical Report of IEICE, pp. DSP96-42, 1996-06-01.
  14. Hiroyuki KOBAYASHI, Hitoshi KIYA,
    "Oversampled DFT Filter Banks with Arbitrary Decimation Ratios and Their Minimum Delays",
    Technical Report of IEICE, pp. DSP96-10, 1996-05-01.
  15. Hiroyuki KOBAYASHI, Takuya YAMAUCHI, Hitoshi KIYA,
    "Oversampled Filter Banks with Arbitrary Delays",
    Society Conference of IEICE, pp. A-74, 1996-09-01.
  16. Katsushige MATSUBARA, Kiyoshi NISHIKAWA, Hitoshi KIYA,
    "Pipelined Adaptive Filters Based on Look-Ahead-Based Delayed LMS Algorithm",
    IEICE Digital Signal Processing Symposium, pp. A6-1, 1996-11-01.
  17. Katsushige MATSUBARA, Kiyoshi NISHIKAWA, Hitoshi KIYA,
    "Pipelined Adaptive Filters based on Two-Dimensional LMS Algorithm",
    General Conference of IEICE, pp. A-142, 1996-03-01.
  18. Yasuhiro HARADA, Shogo MURAMATSU, Hitoshi KIYA,
    "Two-Channel QMF Banks without Checkerboard Effect",
    Technical Report of IEICE, pp. CAS96-52, 1996-09-01.
  19. Tsukasa YAMAMOTO, Takeshi UCHIDA, Hitoshi KIYA, Akihiko YAMADA,
    "ソフトウェア・パイプライニングに基づく演算器の選択法 -記憶要素のコスト削減に関する検討 -",
    IPSJ Design Automation Symposium, 1996-08-01.